The present invention relates to a method of manufacturing a semiconductor device and the semiconductor device, and particularly to a method of manufacturing a semiconductor device including a SRAM and such a semiconductor device.
As a form of a semiconductor device, there is a semiconductor device called a SOC (System On Chip). In a semiconductor device of this type, a plurality of logic circuits, memory cells, and the like are mounted on one chip. A description will be given herein of a semiconductor device in which a SRAM (Static Random Access Memory) is applied to a memory cell of such a semiconductor device.
A SRAM memory cell includes a flip-flop in which two inverters are cross-coupled, and two access transistors. In the flip-flop, two cross-coupled storage nodes are provided. In the two storage nodes, a bi-stable state is present in which the potential at one of the storage nodes is set at a HIGH level, and the potential at the other storage node is set at a LOW level. As long as a predetermined power source potential is applied, the state is held and stored as “1” or “0” as information.
In a typical SRAM memory cell including six transistors, the drive transistors are coupled between the storage nodes and a ground potential, and the load transistors are coupled between the storage nodes and a power source potential. Additionally, between the storage nodes and bit lines, the access transistors are coupled. Data writing and reading is performed via the access transistors.
To ensure a read margin, when data is read, it is required to increase the threshold voltage of each of the access transistors, and increase a ratio (β ratio) of a current in each of the drive transistors to a current in the access transistor. On the other hand, to ensure a write margin, when data is written, it is required to reduce the threshold voltage of the access transistor, and increase the ratio (γ ratio) of the current in the access transistor to a current in each of the load transistors.
As access transistors responding to such requirements, access transistors have been proposed in a SRAM memory cell described in Non-Patent Document 1 in each of which the impurity concentrations of a pair of halo regions are set asymmetrically. That is, the access transistors have been proposed in each of which the impurity concentration of the one of the pair of halo regions coupled to a storage node is set higher than the impurity concentration of the other halo region coupled to a bit line. Note that the halo regions are impurity regions formed in a miniaturized transistor so as to suppress a short channel effect. Ion implantation for forming the halo regions is referred to also as pocket implantation.    [Prior Art Document]    [Non-Patent Document]    [Non-Patent Document 1]
Jae-Joon Kim, Adiya Bansal, Rahul Rao, Shih-Hsien Lo, and Ching-Te Chuang “Relaxing Conflict Between Read Stability and Writability in 6T SRAM Cell Using Asymmetric Transistors” IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 8, August 2009.